Principal-level engineering support when your ASIC program needs experienced help.
I provide hands-on ASIC physical-design consulting for semiconductor and technology companies that need senior engineering support for a difficult design problem, a critical project milestone, or tape-out execution.
My focus is not simply adding another engineer to the project. It is understanding the problem, identifying the real root cause, and helping the team reach closure.
(408) 857-4771
When experience matters more than adding another pair of hands.
Companies usually need principal-level consulting support when the design is technically difficult, the schedule is under pressure, or the team needs someone who can connect multiple parts of the physical-design problem instead of looking at only one flow stage.
The design is not converging
Timing, congestion, clocking, parasitics, power, or signoff issues are interacting and the team needs experienced root-cause analysis.
Tape-out risk is increasing
Critical milestones are approaching and unresolved physical-design or signoff problems need focused technical ownership.
The team needs senior judgment
The issue is no longer about knowing another command. It requires understanding implementation tradeoffs and choosing the path that is most likely to close.
Constraints or timing are questionable
SDC, MMMC, setup/hold behavior, clock paths, ECO results, or signoff correlation need to be reviewed at a principal level.
Implementation and signoff are disconnected
I can work across physical design, STA, power, IR/EM, UPF, and physical verification so fixes are evaluated in the context of the full chip.
You need someone productive quickly
My value is the ability to step into an existing flow, understand what the team is trying to accomplish, identify technical risk, and begin contributing without a long ramp-up period.
Where I can help
Support can be focused on one critical problem or cover a broader portion of the physical-design and signoff flow.
Timing Closure & STA
PrimeTime, Tempus, SDC, MMMC, setup/hold analysis, clock-path debugging, ECO strategy, WNS/TNS reduction, and signoff correlation.
Physical Design Implementation
Floorplanning, placement, CTS, routing, congestion analysis, optimization, physically aware ECO, and RTL/netlist-to-GDSII execution.
Power & Power Integrity
UPF, PrimePower/PT-PX, Voltus, RedHawk, IR/EM analysis, power-grid evaluation, and low-power implementation.
Physical Verification & Signoff
DRC, LVS, DFM, antenna, Calibre, IC Validator, and tape-out readiness.
Design Debug & Recovery
Support for programs that are behind schedule, failing timing, experiencing signoff-correlation problems, or approaching critical tape-out milestones.
EDA Methodology & Automation
Tcl, Python, shell scripting, report analysis, flow automation, methodology improvement, and engineering productivity.
Typical consulting situations
Critical short-term problem
A specific timing, physical-design, power, or signoff issue needs experienced attention quickly.
Timing closure / ECO
The design is late in the schedule and needs focused STA, constraint, ECO, or signoff-correlation support.
Tape-out recovery
The program is approaching tape-out with unresolved implementation, verification, power, or timing risks.
Block or subsystem ownership
A defined physical-design scope needs experienced RTL/netlist-to-GDSII execution and technical ownership.
Technical design review
An independent senior review is needed for constraints, timing strategy, physical design, power, or signoff readiness.
Team augmentation
A project needs principal-level hands-on engineering support for a defined period or milestone.
Structured around the engineering problem.
Consulting engagements can be organized around a defined technical problem, project milestone, deliverable, or agreed engineering scope.
- Clarify the technical objective and success criteria.
- Review the relevant design, constraints, reports, and flow conditions.
- Identify root causes and technical risks.
- Define and execute the engineering path toward closure.
- Document conclusions, recommended actions, and remaining risks.
Have a difficult ASIC problem?
If your program has a physical-design, timing, power, or signoff problem that needs experienced hands, contact me directly. I can discuss the technical problem, the project stage, and what kind of engagement would make sense.