I help teams get difficult ASICs to closure.
I bring more than 30 years of semiconductor engineering experience to complex physical-design programs—especially when timing, constraints, power, implementation, and signoff stop behaving like separate problems.
What I can do for your ASIC program
My role is not simply to run a flow. It is to find the real reason a design is not converging, make the right engineering tradeoffs, and help move the program toward signoff and tape-out.
Own difficult implementation problems
Work across floorplanning, placement, CTS, routing, ECO, congestion, and signoff instead of treating them as isolated tasks.
Drive timing closure
PrimeTime, Tempus, SDC, MMMC, setup/hold analysis, clock-path behavior, ECO strategy, and signoff correlation.
Connect timing, power, and physical reality
UPF, PrimePower/PT-PX, Voltus, RedHawk, IR/EM, parasitics, and implementation decisions that affect signoff.
Improve engineering execution
Tcl, Python, shell, flow automation, methodology development, debug discipline, and cross-functional technical leadership.
How I think about physical design
Practical articles on timing closure, constraints, ECO, floorplanning, power, signoff, and lessons learned through repeated tape-outs.
Timing Closure Is Not Just Fixing Negative Slack
Published
The Last 100 ps: Why Late-Stage Timing Closure Is So Difficult
Published
Before Fixing a Timing Violation, Make Sure It Is a Real Violation
Available Monday, September 21, 2026
Floorplanning Decisions You Pay for During Timing Closure
Available Monday, September 28, 2026
How I Debug a Timing Violation Before Touching the Netlist
Available Monday, October 5, 2026
SDC Quality Can Make or Break Physical Design
Available Monday, October 12, 2026
MMMC: Why More Scenarios Do Not Automatically Mean Better Signoff
Available Monday, October 19, 2026
Clock Trees: Skew Is Only Part of the Problem
Available Monday, October 26, 2026
When Should You Fix Timing in P&R vs. PrimeTime ECO?
Available Monday, November 2, 2026
IR Drop and Timing Closure Are More Connected Than Many Designers Think
Available Monday, November 9, 2026
UPF Problems That Become Physical-Design Problems
Available Monday, November 16, 2026
Congestion, Timing, and Power: The Three-Way Tradeoff in Advanced Nodes
Available Monday, November 23, 2026
What 19+ Tape-outs Teach You That a Flow Manual Does Not
Available Monday, November 30, 2026
Can AI Really Help Close Timing? A Physical Designer’s Perspective
Available Monday, December 7, 2026
What Makes a Physical Design Engineer Principal-Level?
Available Monday, December 14, 2026
Short ASIC physical-design discussions
Watch concise video discussions based on real implementation experience in timing closure, floorplanning, constraints, MMMC, power, signoff, and related physical-design topics.
View Technical VideosEngineering insight in a short-format presentation
Each video highlights the main engineering lesson, with the full technical article available for deeper detail.
Watch the Series →Principal-level physical design coverage
RTL / Netlist to GDSII
Floorplanning, placement, CTS, routing, optimization, ECO, physical verification, signoff, and tape-out.
STA & Timing Closure
PrimeTime, Tempus, SDC, MMMC, setup/hold closure, clock analysis, WNS/TNS, and timing ECO.
Power & Low Power
PrimePower/PT-PX, Voltus, RedHawk, UPF, dynamic/leakage analysis, and IR/EM.
Physical Verification
Calibre, IC Validator/VUE, DRC, LVS, ERC, DFM, antenna, and tape-out readiness.
Advanced Nodes
Experience across multiple technology generations, including TSMC designs down to 4nm.
EDA Automation
Tcl, Python, shell, Makefile, SED/AWK, and methodology development for repeatable execution.
Research depth. EDA breadth. Production tape-out experience.
My career spans IBM Research, EDA companies, semiconductor organizations, and advanced technology programs. That range matters because difficult physical-design problems rarely belong to one tool or one flow stage.
The complete employment history, education, certifications, and client engagements remain in the résumé so the landing page stays focused on what I can do for a client.
View Full ResumeInterested in working with me through Athena Cloud Engineers?
I am building a network of experienced engineers who can support client ASIC programs in physical design, STA, power, verification, automation, and related semiconductor disciplines.
Need experienced hands on a difficult ASIC?
If your program needs principal-level physical-design judgment, timing-closure depth, signoff experience, or help resolving a design that is not converging, contact me.