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Ruben Reyes
ASIC Physical Design • Timing/Power • ML/AI
Business-grade engineering portfolio
Ruben Reyes

Principal ASIC Physical Design Engineer with deep timing/power signoff experience and a practical ML/AI track for EDA automation.

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RTL→GDSII STA / MMMC PrimePower / PT-PX UPF low power IR/EM signoff TSMC 4nm/5nm

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What I deliver

Execution-first: predictable closure, clean signoff, and automation that sticks.

RTL to GDSII closure flow diagram mockup

Timing closure

PrimeTime-driven WNS/TNS closure, clock/path optimization, MMMC constraints, and signoff-quality reporting.

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Power and IR drop visualization mockup

Power & low-power

PrimePower/PT-PX, UPF multi-domain implementation, isolation/retention/LS, and power-state verification.

Services →
AI for EDA closure predictor loop mockup

ML/AI for EDA automation

Practical automation using Python + data pipelines to reduce iteration time and improve closure predictability.

Resume →