Principal ASIC Physical Design Engineer

Ruben Reyes

I help semiconductor teams get difficult ASICs to timing closure, signoff, and tape-out.

My value is not just knowing the tools. I bring end-to-end physical-design judgment across RTL/netlist-to-GDSII, STA and SDC, timing closure, low power, power integrity, physical verification, ECO, and signoff - with hands-on experience across advanced technology nodes down to TSMC 4nm.

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What I can do for your ASIC program

I am most valuable when the design is complex, the schedule matters, and the problem crosses more than one physical-design discipline.

Own difficult implementation problems

Work from synthesized RTL or netlist through floorplanning, placement, CTS, routing, optimization, ECO, physical verification, signoff, and foundry-ready GDSII.

Drive timing closure

Analyze and resolve setup/hold, clock-path, SDC, MMMC, WNS/TNS, and late-stage timing issues using PrimeTime, Tempus, implementation tools, and physically aware ECO flows.

Connect timing, power, and physical reality

Resolve problems where constraints, placement, routing, parasitics, UPF, power integrity, or signoff interact instead of treating each flow stage as a separate problem.

Improve engineering execution

Develop practical Tcl, Python, shell, Makefile, and EDA methodology improvements that make debug, reporting, correlation, and repeated design work more efficient and reliable.

Principal-level technical scope

Broad enough to see the complete physical-design system, deep enough to work directly on the problem.

Physical Design

RTL/netlist-to-GDSII, floorplanning, placement, CTS, routing, optimization, ECO, tape-out.

STA & Constraints

PrimeTime, Tempus, SDC, MMMC, setup/hold, clock analysis, timing ECO, constraint debug.

Power & Low Power

UPF, PrimePower/PT-PX, Voltus, RedHawk, dynamic/leakage power, power domains, IR/EM.

Physical Verification

Calibre, IC Validator/VUE, DRC, LVS, ERC, DFM, antenna, signoff readiness.

EDA Platforms

Fusion Compiler, ICC2, Design Compiler, Innovus, Genus, PrimeTime, Tempus, Voltus, StarRC, Formality, Conformal.

Automation & Methodology

Tcl, Python, shell, Makefile, SED/AWK, flow automation, report analysis, methodology development.

A career built across semiconductor research, EDA, production silicon, and advanced-node tape-out.

AmazonMetaGoogleMicrosoftBroadcomIntelAMDSynopsysCadenceIBM Research

I began my career in IBM Research and have worked through multiple generations of semiconductor technology, EDA methodology, and production ASIC implementation. That breadth is useful because the hardest physical-design problems usually do not respect organizational boundaries.

I have worked on CPUs, DDR/DDR5, NOC, VP9/H.264, graphics, PCIe, GDDR, AI/ML compute, mixed-signal designs, and other SoCs. My recent work includes advanced-node timing, SDC, power, and physical-design engagements through Athena Cloud Engineers.

Education: M.S. Electrical Engineering, Polytechnic University; B.S. Electrical Engineering with Honors, Pratt Institute. Additional professional education includes applied machine learning, AI, and Python through Cornell.

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Technical Articles

Practical notes on ASIC physical design, timing closure, signoff, methodology, and the engineering judgment required to bring difficult designs to tape-out.

01Timing Closure Is Not Just Fixing Negative SlackPublished 02The Last 100 ps: Why Late-Stage Timing Closure Is So DifficultComing Soon 03Before Fixing a Timing Violation, Make Sure It Is a Real ViolationComing Soon 04Floorplanning Decisions You Pay for During Timing ClosureComing Soon 05How I Debug a Timing Violation Before Touching the NetlistComing Soon 06SDC Quality Can Make or Break Physical DesignComing Soon 07MMMC: Why More Scenarios Do Not Automatically Mean Better SignoffComing Soon 08Clock Trees: Skew Is Only Part of the ProblemComing Soon 09When Should You Fix Timing in P&R vs. PrimeTime ECO?Coming Soon 10IR Drop and Timing Closure Are More Connected Than Many Designers ThinkComing Soon 11UPF Problems That Become Physical-Design ProblemsComing Soon 12Congestion, Timing, and Power: The Three-Way Tradeoff in Advanced NodesComing Soon 13What 19+ Tape-outs Teach You That a Flow Manual Does NotComing Soon 14Can AI Really Help Close Timing? A Physical Designer’s PerspectiveComing Soon 15What Makes a Physical Design Engineer Principal-Level?Coming Soon

Need an experienced engineer to help close a difficult ASIC?

For principal-level physical design, STA/SDC, timing closure, power/signoff, methodology, or advanced-node implementation work, contact me directly.

Ruben.Reyes@AthenaCloudEngineers.com (408) 857-4771 Resume